Asynchronous circuits

Most digital design uses clocks to ensure that everything works in the correct manner. The major idea here is that the system will be correct after everything has settled out (electrons travel through wires, transistors turn on, all the gates complete their functions). The major issue here is that our clock has to be slow enough that the slowest process in our circuit has time to finish. So what's the solution?

Asynchronous design. The idea here is that instead of having a clock tick once everything must be valid, each module can tell the next module when it's ready. In other words, the paradigm shifts from a global clock to many local 'handshakes.' I really want to just get to the cool parts - so hopefully this won't lose people...

Let's say there are two modules. A is the sender and B is the receiver. We'd like to get some data from A to B, but only once B is ready for it. So let's say A is ready to send. I'll run through two schemes...

Bundled Data scheme (with active sender):

In this scheme, A pulls the req wire high to let B know that the data line is valid. Then B uses the data and sets its ack line high. When A sees the acknowledge go high, it sets the request line back down to 0. B responds by setting the ack line to 0. So after all of this, the ack and req lines are back to 0 and all's good. It's worth noting that there could be any number (N) of data bits here for a total of N+2 wires.

So there's one issue with this. When A's data becomes valid, it sets request high... but what happens if B sees the req line go high before the valid data travels all the way down to be. These things all have finite speeds, so in the end we get designs that can move electricity faster down the data line(s) in order to get around the race condition.


DI Dual Rail scheme (with active sender):

So here's a set-up that avoids the race condition entirely. Ass such, it qualifies as truly DI (delay insensitive). The idea here is that A has both the true line and the false line low - this is its null state and indicates it has no data. Now when A pulls a line high, B knows what the data is and that it's valid... ZOMG! Once B has used the data, it lets A know by raising the ack line. A responds by returning to the null state and then B responds by lowering its ack line. Now everything is back where it started and we avoided the race condition!

But wait. This is engineering. I wouldn't have bothered telling y'all about the bundled scheme if it was always worse. The tradeoff is in the number of wires. N bits will take 2N + 1 wires to implement in a DI dual rail scheme.

Neat.